VALIDATION AND TEST TIME REDUCTION APPROACH FOR BUILTIN-SELF-TEST AND REPAIR OF MEMORIES VIA A SHARED INTERFACE

Abstract

A memory built-in self-test and repair (MBISTR) is a key component in improving a system-on chip (SoC) yield under daily raising new challenges in IC industry where memories very often make up the bulk of a SoC. Once a given SoC has a huge number of memories, it is convenient to test them via a common test network. Meantime, some designs do not allow to insert this network into an already existing functional design via adding new nodes in the existing paths but do allow to add it to the design via already existing functional connection interfaces instead. For example, a shared interface for connecting a central processing unit (CPU) and cache memories in SoCs is already used for testing these memories via special MBISTR engines connected to this shared interface. These MBISTR engines have specific features which may impact essentially the validation and test time. A way for validation and test time reduction is proposed in this paper for the multiport memories connected to MBISTR engine via a shared interface.