Effect of Through-Silicon-Via Joule Heating on Device Performance for Low-Powered Mobile Applications-Reference-Cited by-同舟云学术

Effect of Through-Silicon-Via Joule Heating on Device Performance for Low-Powered Mobile Applications

Published:2014-09-19 Issue:4 Volume:136 Page:
ISSN:1043-7398
Container-title:Journal of Electronic Packaging
language:en
Short-container-title:

Author:

Mirza Fahad¹,Naware Gaurang¹,Jain Ankur²,Agonafer Dereje³

Affiliation:

1. Mechanical and Aerospace Engineering, University of Texas at Arlington, 500 W First Street, Woolf Hall Mechanical Engineering, Room 211, Arlington, TX 76019 e-mail:

2. Mechanical and Aerospace Engineering, University of Texas at Arlington, 500 W First Street, Engineering Lab Building, Room 203, Arlington, TX 76019 e-mail:

3. Mechanical and Aerospace Engineering, University of Texas at Arlington, 500 W First Street, Woolf Hall Mechanical Engineering, Room 211, Arlington, TX 76019 e-mail:

Abstract

Three-dimensional (3D) through-silicon-via (TSV) technology is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. TSVs provide high speed signal propagation due to reduced interconnect lengths as compared to wire-bonding. The current flowing through the TSVs results in localized heat generation (joule heating), which could be detrimental to the device performance. The effect of joule heating on performance measured by transconductance, electron mobility (e− mobility), and channel thermal noise is presented. Results indicate that joule heating has a significant effect on the junction temperature and subsequently results in 10–15% performance hit.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Link

http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/doi/10.1115/1.4028076/6140711/ep_136_04_041008.pdf

Reference21 articles.

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2. Interstratum Connection Design Considerations for Cost Effective Three-Dimensional (3D) System Integration;IEEE Trans. VLSI Syst.,2010

3. Through-Silicon Via 3D Integration

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