Controlling the Solder Joint Reliability of eWLB Packages in Automotive Radar Applications Using a Design for Reliability Approach

Author:

Niessner M.1,Haubner G.2,Hartner W.2,Pahlke S.2

Affiliation:

1. Infineon Technologies AG, Neubiberg, Germany

2. Infineon Technologies AG, Regensburg, Germany

Abstract

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

Publisher

American Society of Mechanical Engineers

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Application of Digital Image Correlation (DIC) for deformation measurement of fan-out Wafer Level Package mounted on Printed Circuit Board;2024 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE);2024-04-07

2. Deformation measurement on cross sections of Fan-Out Wafer Level Package by Digital Image Correlation (DIC);2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC);2022-09-13

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