Affiliation:
1. The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
Abstract
Conventional flip chip on board processing involves four major steps: flux application, solder reflow, underfill flow, and underfill cure. The latter two steps are particularly time consuming. To address this issue, a new flip chip process has been developed in which underfill is dispensed prior to chip placement or directly on the wafer and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacturing. However, the presence of the underfill can affect the flip chips’ capacity for self-alignment. Self-alignment occurs in controlled collapse bonding when the solder interconnects become liquidus and, driven by surface tension, pull the chip into registration with the substrate. To study flip chip self-alignment in the presence of underfill, the viscous forces acting on the chip during realignment are modeled after Couette flow and the overall system is modeled as a spring-mass-damper. This paper details the modeling process and includes parametric studies to predict those conditions that are more conducive to alignment, as well as those which are not.
Subject
Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials
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