A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints-Reference-Cited by-同舟云学术

A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints

Published:2002-07-26 Issue:3 Volume:124 Page:212-220
ISSN:1043-7398
Container-title:Journal of Electronic Packaging
language:en
Short-container-title:

Author:

Lau John H.¹,Pan Stephen H.¹,Chang Chris¹

Affiliation:

1. Agilent Technologies, Inc., 350 W. Trimble Road, MS 90LJ, San Jose, CA 95131

Abstract

A new empirical equation for predicting the thermal-fatigue life of wafer level chip scale package (WLCSP) solder joints on printed circuit board (PCB) is presented. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the average strain energy density around the crack tip of different crack lengths in the corner solder joint is determined by a time-dependent nonlinear fracture mechanics with finite element method. The solder is assumed to be a temperature-dependent elastic-plastic and a time-dependent creep material.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Link

http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/124/3/212/5802770/212_1.pdf

Reference16 articles.

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2. Lau, J. H., and Lee, S. W., 2001, Microvias for Low Cost, High Density Interconnects, McGraw-Hill, New York, NY.

3. Lau, J. H., and Lee, S. W., 1999, Chip Scale Package: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, NY, 1999.

4. Nguyen, L., N., Kelkar, and Takiar, H., 2000, “A Manufacturing Perspective of Wafer Level CSP,” IEEE Proceedings of Electronic Components & Technology Conference, May, pp. 97–100.

5. Topper, M., Auersperg, J., Glaw, V., Kaskoun, K., Prack, E., Keser, B., Coskina, P., Jager, D., Petter, D., Ehrmann, O., Samulewicz, K., Meinherz, C., Fehlberg, S., Karduck, C., and Reichl, H., 2000, “Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging,” IEEE Proceedings of Electronic Components & Technology Conference, May, pp. 74–80.

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