Analytical Thermo-Mechanical Model for Non-Underfilled Area Array Flip Chip Assemblies

Author:

Vandevelde Bart1,Beyne Eric1,Vandepitte Dirk2,Baelmans Martine2

Affiliation:

1. IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

2. Catholic University of Leuven, Celestijnenlaan 300B, B-3001 Leuven, Belgium

Abstract

An analytical model is derived for the calculation of thermo-mechanical induced stresses in area array flip chip assemblies. This analytical model is based on structural mechanics and has the ability to characterize the nature and to estimate the magnitude of the induced stresses. The extension of this model compared to existing procedures is its applicability to area array systems, which behave significantly different from peripheral assemblies. The model is compared to finite element simulations. The model calculates accurately the forces and bending moments acting on the flip chip connections. The transformation of these forces and moments into stresses is less accurate as the model does not include stress concentrations near the corners. The model simulates very well the different parameter trends such as chip size and is therefore well suited for understanding parameter sensitivity studies.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. The Nordic Electronics Packaging Guideline, http://extra.ivf.se/ngl

2. Vandevelde, B., Beyne, E., Vandepitte, D., and Baelmans, M., 2002, “Semi-Analytical Model for Calculation of Induced Strains in Solder Joints of Underfilled Flip Chip Assemblies,” Proceedings of the 3rd Eurosime conference, pp. 86–91, Paris, France, April 14–17.

3. Vandevelde, B., Christiaens, F., Beyne, E., Peeters, J., Allaert, K., Vandepitte, D., and Berghmans, J., 1998, “A Thermo-Mechanical Model for Leadless Solder Interconnections in Flip Chip Assemblies,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 21, pp. 177–185.

4. Suhir, E., 1988, “Thermal Stress Failures in Microelectronic Components—Review and Extension,” Advances in Thermal modelling of Electronic Components and Systems, A. Bar-Cohen and A. D. Kraus, eds., New York, Hemisphere, Vol. 1, Ch. 5, pp. 337–412.

5. Tummala, R. R., and Rymaszewski, E. S., 1989, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York.

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