Recent Advances and Trends in Chiplet Design and Heterogeneous Integration Packaging

Author:

Lau John H.1

Affiliation:

1. Unimicron Technology Corporation , No. 179, Shanying Rd., Taoyuan City 33341, Taiwan

Abstract

Abstract In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield, Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference233 articles.

1. 3D V-CacheTM: The Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7 nm × 86-64 CPU,2022

2. 3D Packaging for Heterogeneous Integration,2022

3. The Next Frontier: Enabling Moore's Law Using Heterogeneous Integration;Chip Scale Rev.,2022

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