A Study on Warpage of Flexible SS Substrates for Large Area MCM-D Packaging

Author:

Dang Anh X. H.1,Ume I. Charles1,Bhattacharya Swapan K.2

Affiliation:

1. School of Mechanical Engineering, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332

2. Packaging Research Center, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332

Abstract

This paper presents potential application of stainless steel (SS) as a base substrate material for large area multi-chip module-deposited (MCM-D) packaging. Preliminary results on via formation on SS substrates by laser drilling, dielectric coating on SS surface and on via sidewall, via filling for front-to-back interconnects, and subsequent curing of via filling material are reported in this paper. The objective of this DARPA funded MCM-D Consortium is to investigate the feasibility of application of stainless steel materials for large area MCM-D packaging through laboratory prototypes and simulated thin film process. This paper particularly addresses the warpage issues related to via formation, dielectric coating on the substrates, and via filling process after substrates were exposed to temperatures above 130 °C for two hours. The change in process induced warpage was quantified by the simple non-destructive Shadow Moire´ technique. The end objective of this work is to be able to fabricate large area 24 in.×24 in.SS substrates with minimum warpage. The study shows that SS can be a candidate substrate for large area MCM-D packaging. [S1043-7398(00)00702-7]

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. Tummala, R. R., Nandakumar, G. A., Bolda, F., and Klopfenstein, A., 1997, Microelectronic Packaging Handbook, Chap. 18, Chapman & Hall, London.

2. Padmadinata, F. Z., Veerhoek, J. J., Van Dijk, G. J. A., and Huijsing, J. H., 1990, “Microelectronic Skin Electrode,” Sens. Actuators B, B1, pp. 491–49.

3. Dang, A., Ume, I. C., and Bhattacharya, S., 1999, “In-Situ Warpage Measurement during Thermal Cycling of Dielectric Coated SS Substrates,” ASME Conference, Tennessee. The ASME International Mechanical Engineering Conference and Exposition, November 14–19, 1999, Nashville, TN.

4. Southerlin, S., Polsky, Y., and Ume, C., 1998, “Relative Comparison of PWB Warpage Due to Simulated Infrared and Wave Soldering Processes,” Proceedings 48th IEEE Electronic Components and Technology Conference, pp. 807–815.

5. Polsky, Y., Ume, C., and Southerlin, W., 1998, “Application of Thermoelastic Lamination Theory to Predict Warpage of a Symmetric and Simply Supported PWB During Temperature Cycling,” Proceedings 48th IEEE Electronic Components and Technology Conference, pp. 345–352.

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