Thermo-Viscoelastic Analysis of Deflection in CSP Electronic Device Packages-Reference-Cited by-同舟云学术

Thermo-Viscoelastic Analysis of Deflection in CSP Electronic Device Packages

Published:2003-09-01 Issue:3 Volume:125 Page:414-419
ISSN:1043-7398
Container-title:Journal of Electronic Packaging
language:en
Short-container-title:

Author:

Koguchi Hideo¹,Sasaki Chie²,Nishida Kazuto²

Affiliation:

1. Nagaoka University of Technology, 1603-1 Kamitomioka, Nagaoka, Niigata, 940-2188, Japan

2. Matushita Electric Industrial Co., LTD. 2-7, Matsuba-cho, Kadoma, Osaka, 576-0053, Japan

Abstract

In the present paper, a deformation induced in a new bonding technology of chip-scale package (CSP) using resin encapsulation sheets is examined numerically and experimentally. Deflections after cooling from a bonding temperature are measured experimentally for various kinds of substrate and the thickness of an integrated circuit using a laser beam. In particular, a simple theory on the basis of a multilayered plate theory considering a viscoelastic property in the substrate is presented, and the thermo-viscoelastic analysis for the deflection of CSP is performed. Furthermore, the thermo-elastoplastic finite element method analysis is performed under the same temperature history. We could show that the simple formula for multilayered plates based on the thermo-viscoelatic theory can estimate fairly well the deflection of CSP in experiment.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Link

http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/125/3/414/5883899/414_1.pdf

Reference25 articles.

1. Iwatsu, S., and Honda, N., 2001, “Reliability Analysis for Underfill-Encapsulated Flip Chip Packages (Direct Attach Aurum Bump Type),” JIEP Journal of Japan Institute Electronics Packaging, 4, pp. 515–518.

2. Saito, K., Hayashi, S., Takahashi, H., and Yamagata, M., 2000, “Flow Analysis of Non Conductive Resin Paste for Flip Chip Interconnection Process,” Proceedings of 2000 International Symposium on Microelectronics, pp. 343–346.

3. Tamaki, K., Saza, Y., Dotta, Y., and Rai, A., 1999, “Development of Stacked CSP using Flip-Chip Technologies,” Proceedings of the 1999 International Symposium on Microelectronics, pp. 33–36.

4. Nakamura, S., Kido, M., Kushizki, Y., Murakami, G., and Mita, M., 2000, “Thermo-viscoelastic Numerical Analysis of Residual Stress in a Semiconductor Device against its Material Properties,” Proceedings of 2000 International Symposium on Microelectronics, pp. 331–334.

5. Nishida, K., Nishikawa, H., and Ohtani, H., 1999, “Flip-Chip Bonding Technology using a Resin Encapsulation Sheet,” Proceedings of the 6th Symposium on Microjoining and Assembly Technology in Electronics (MATE ‘99), pp. 189–192.

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