Review on Percolating and Neck-Based Underfills for Three-Dimensional Chip Stacks
Author:
Brunschwiler Thomas1, Zürcher Jonas1, Del Carro Luca1, Schlottig Gerd1, Burg Brian1, Zimmermann Severin1, Zschenderlein Uwe2, Wunderle Bernhard2, Schindler-Saefkow Florian3, Stässle Rahel1
Affiliation:
1. IBM Research—Zurich, Säumerstrasse 4, Rüschlikon 8803, Switzerland e-mail: 2. Department of Materials and Reliability of Microsystems, Technical University of Chemnitz, Reichenhainer Street 70, Chemnitz 09126, Germany e-mail: 3. AMIC—Angewandte Micro-Messtechnik GmbH, Säumerstrasse 4, Volmerstraße 9, Berlin 12489, Germany e-mail:
Abstract
Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.
Publisher
ASME International
Subject
Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials
Reference31 articles.
1. Toward Five-Dimensional Scaling: How Density Improves Efficiency in Future Computers;IBM J. Res. Develop.,2011 2. Iyer, S. S., 2012, “The Evolution of Dense Embedded Memory in High Performance Logic Technologies,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 10–13, pp. 33.1.1–33.1.4.10.1109/IEDM.2012.6479155 3. Jeddeloh, J., and Keeth, B., 2012, “Hybrid Memory Cube New DRAM Architecture Increases Density and Performance,” Symposium on VLSI Technology (VLSIT), Honolulu, HI, June 12–14, pp. 87–88.10.1109/VLSIT.2012.6242474 4. A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters;Solid-State Circuits,2015 5. Zhao, J., Sun, G., Loh, G. H., and Xie, Y., 2012, “Energy-Efficient GPU Design With Reconfigurable In-Package Graphics Memory,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12), Redondo Beach, CA, Aug. 8–10, pp. 403–408.10.1145/2333660.2333752
Cited by
13 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|