Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging-Reference-Cited by-同舟云学术

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

Published:2002-07-26 Issue:3 Volume:124 Page:234-239
ISSN:1043-7398
Container-title:Journal of Electronic Packaging
language:en
Short-container-title:

Author:

Lin Y. T.¹,Peng C. T.¹,Chiang K. N.¹

Affiliation:

1. Dept. of Power Mechanical Engineering, National Tsing Hua University, HsinChu 30013, Taiwan

Abstract

The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder interconnection, such as wire interconnect technology (WIT). New technology, which uses copper posts to replace the solder bumps as interconnections, has improved reliability. Moreover, this type of wafer level package produces higher I/O density, as well as ultra fine pitch. This research focuses on the reliability analysis, material selection and structural design of WIT packaging. This research employs finite element method (FEM) to analyze the physical behavior of packaging structures under thermal cycling conditions to compare the reliability characteristics of conventional wafer level and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature-dependent material properties will be applied to all models.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Link

http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/124/3/234/5801959/234_1.pdf

Reference15 articles.

1. Elenius, P., 1998, “The UltraCSP Wafer Scale Package,” IEEE/CPMT Electronics Packaging Technology Conference, Proceedings of 2nd, pp. 83–88, Dec. 8–10, Singapore.

2. Wang, J., Qian, Z., Zou, D., and Liu, S., 1998, “Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moire´ Interferometry,” Proceeding of Electronic Components and Technology Conference, 48th, Seattle, WA, USA, pp. 1438–1445, May 25–28.

3. Daveaux, R., and Benerji, K., 1991, “Fatigue Analysis of Flip Chip Assemblies Using Thermal Stress Simulations and a Coffin-Manson Relation,” 10569-5503/91/0000-0797 IEEE, pp. 797–805.

4. Goodman, T., and Elenius, P., 1997, “Flex-On-Cap Solder Paste Bumping,” Electronic Components and Technology Conference ’97, pp. 248–253.

5. Collins, J. A., 1984, “Failure of Materials in Mechanical Design—Analysis, Prediction, Prevention,” pp. 384–387.

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