Evaluation of Relationship between Residual Stress on Chip Using Non-Conductive Film and Package Warpage Caused by Flip-Chip Bonding Process Using Test Element Group Chips with Piezoresistive Sensors

Author:

Enami Toshio12,Horiuchi Osamu3,Han Young-Gun3,Tomokage Hajime23

Affiliation:

1. R&D Institute High Performance Plastics Company, Sekisui Chemical Co., Ltd.

2. Department of Electronic Engineering and Computer Science, Fukuoka University

3. Center of System Integration Platform Organization Standards (CSIPOS), Fukuoka University

Publisher

Japan Institute of Electronics Packaging

Reference20 articles.

1. [1] Japan Jisso Technology 2007, Japan Electronics and Information Technology Industries Association, 2007.

2. [2] Y. Shimada, "Advanced Packaging Technology Trend and Future Prospects (in Japanese)," The Institute of Electronics, Information and Communication Engineers (C), Vol. J88-C, No. 11, pp. 827-838, 2005.

3. [3] M. Mizukoshi, "Newest Flip Chip Bonding Technology (in Japanese)," The Japan Institute of Electronics Packaging, Vol. 10, No. 5, pp. 415-422, 2007.

4. [4] R. Haruta, "Packaging Technology Trend (in Japanese)," The Japan Institute of Electronics Packaging, Vol. 10, No. 5, pp. 353-357, 2007.

5. [5] T. Sasaki, H. Ueda, and H. Miura, "Measurement of Local Two Dimensional Stress Distribution in a Flip Chip Structure by Using Strain Sensor Chips with 2 μm Long Piezoresistance Gauges (in Japanese)," The Japan Institute of Electronics Packaging, Vol. 12, No. 7, pp. 623-628, 2009.

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