Advanced Plating Photoresist Development for Semiconductor Packages
Author:
Affiliation:
1. Advanced Electronic Materials Laboratory, Fine Electronic Materials Research Laboratories, Yokkaichi Research Center, JSR Corporation
Publisher
Japan Institute of Electronics Packaging
Link
https://www.jstage.jst.go.jp/article/jiepeng/9/0/9_E15-007-01/_pdf
Reference7 articles.
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2. [2] Y. Kurita, "A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology," 2007 ECTC, p. 821, 2007.
3. [3] S. W. Yoon, L. Yaojian, S. Gaurav, J. Yonggang, V. P. Ganesh, T. Meyer, P. C. Marimuthu, X. Baraton, and A. Bahr, "Mechanical Characterization of Next Generation eWLB (embedded Wafer Level BGA) Packaging," ECTC, pp. 441-446, 2011.
4. [4] M. Santarini, "Stacked and Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs," Xcell Journal, No. 74, pp. 8-13, 2011.
5. [5] M. Murugesan, H. Kino, H. Nohira, J. C. Bea, A. Horibe, F. Yamada, C. Miyazaki, H. Kobayashi, T. Fukushima, T. Tanaka, and M. Koyanagi, "Wafer Thinning, Bonding, and Interconnects Induced Local Strain/Stress in 3D-LSIs with Fine-Pitch High-Density Microbumps and Through-Si Vias," IEDM, pp. 2.3.1-2.3.4, December 2010.
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