Nondestructive Inspection and Inline Estimation of Profiles of Copper-Filled Through-Silicon Vias with Voids by a Nano-Focus X-ray Microscope
Author:
Affiliation:
1. Tokyo Electron Limited
2. Graduate School of System Design, Tokyo Metropolitan University
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/jiep/20/7/20_468/_pdf
Reference19 articles.
1. 1) S. Kumar: “3DIC and 2.5D TSV Interconnect for advanced packaging: 2016 business update,” Yole development Market & Technology report, September, 2016
2. 2) M. Nagai, Y. Tmari, S. Yasuda, M. Shimoyama, N. Saito, and F. Kuriyama: “Copper Electroplating of High Aspect Ratio Through-silicon Via for 3D Packaging using an UFP Tool,” Ebara annual technical report, No. 230, pp. 7-13 2011
3. 3) V. Vartanial, R. A. Allen, L. Smith, K. Hummler, S. Olson, and B. Sapp: “Metrology needs for though-silicon via fabrication,” J. Micro/Nanolith. MEMS MOEMS., Vol. 13, No. 1, 011206, Feb, 2014
4. 4) L. W. Kong, P. Krueger, E. Zchech, A. C. Rudack, S. Arkalgud, and A. C. Diebold: “Sub-imaging Techniques for 3D-Interconnects On Bonded Wafer Pairs,” 11th International Workshop on Stress-Induced Phenomena in Metallization, pp. 221-228, 2010
5. 5) M. Murugesan, H. Kino, H. Nohira, J. C. Bea, A. Horibe, F. Yamada, C. Miyazaki, H. Kobayashi, T. Fukushima, T. Tanaka, and M. Koyanagi: “Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias,” Electron Devices Meeting (IEDM), IEEE Int., pp. 2.3.1-2.3.4, 2010
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