Author:
Fukushima Takafumi,Tanaka Tetsu,Koyanagi Mitsumasa
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Reference21 articles.
1. 1) M. Koyanagi: “Roadblocks in Achieving Three-Dimensional LSI”, Proc. 8th Symposium on Future Electron Devices, pp. 50–60, 1989
2. Future system-on-silicon LSI chips
3. Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
4. 4) H. Kikuchi, Y. Yamada, H. Kijima, T. Fukushima and M. Koyanagi: “Deep-Trench Etching for Chip-to-Chip Three-Dimensional Integration Technology”, Jap. J. Appl. Phys., Vol. 45, No. 4B, pp. 3024–3030, 2006
5. 5) N. Tanaka, Y. Yoshimura, T. Naito and T. Akazawa: “Silicon Through-Hole Interconnection for 3D-SiP Using Room Temperature Bonding”, Mater. Res. Soc. (MRS) Symp. Proc., Vol. 970, pp. 125–131, 2006
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Development Trend of Three-Dimensional (3D) Integration Technology;IEEJ Transactions on Sensors and Micromachines;2011
2. モバイル端末技術の進化;IEICE Communications Society Magazine;2011