A Simulation Methodology for RISC Computer Systems

Abstract

This paper presents a simulation methodology for evaluating the performance of single and multiprocessor Reduced Instruction Set computers, RISC. The uniprocessor RISC model considers all interactions among various units in the CPU for a wide spectrum of application programs and conditions. The instruction flow of each instruction is modeled and data dependencies and stalls in the different pipelines are considered and treated. The single processor detailed model is used in the Crossbar and Delta-based multiprocessor models. Benchmark programs are characterized by their Input/Output ratio (α). A comparative simulation performance study of crossbar switch and Delta-based multiprocessors using RISC processors is made. The MC88100 RISC processor is considered as a case study for both cases. Different simulation experiments have been carried out to predict the behavior of the single and multiprocessor systems if certain parameters or conditions are varied or satisfied.