Affiliation:
1. Department of Electrical Engineering, Convent Avenue at 140th street, City University of New York, The City College, New York, NY
Abstract
This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8K, the performance of the system is considerably limited by the service time of BIU(Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16K, 32K, 64K, and 128K the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.
Publisher
Association for Computing Machinery (ACM)
Reference20 articles.
1. A Simulation Methodology for RISC Computer Systems
2. Performance simulation analysis of RISC-based multiprocessors under uniform and nonuniform traffic
3. 3
. M.S. Obaidat "Simulation of Queuing Models in Computer Systems "Queuing theory and Application S. Ozekici (ed.) pp. 111-151 Hemisphere publishing company 1990. 3. M.S. Obaidat "Simulation of Queuing Models in Computer Systems "Queuing theory and Application S. Ozekici (ed.) pp. 111-151 Hemisphere publishing company 1990.
4. RISC watch