A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry

Author:

Ameziane Hatim1,Zared Kamal1,Qjidaa Hassan1

Affiliation:

1. Physics Department- Ced-st, Lessi, Faculty of Sciences Sidi Mohamed Ben Abdellah University Bp 1796, 30003 Fez Morocco

Abstract

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

Publisher

World Scientific and Engineering Academy and Society (WSEAS)

Subject

Electrical and Electronic Engineering

Reference12 articles.

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5. H. Ameziane,H.Akhamal, K. Zared, H. Qjidaa “Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems” International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 6: December 2019 .

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