1. 1) http://www.itrs.net/
2. 2) N. Watanabe, T. Kojima and T. Asano : Wafer Level Compliant Bump for Three-Dimensional LSI with High-Density Area Bump Connections, 2005 Int. Electron Devices Meeting (IEDM2005), Technical Digest, (2005) 687.
3. 3) N. Watanabe, T. Higashimachi and T. Asano : Deformation Analysis of Au Cone Bump in 3D LSI Stacking, Dig. Papers Microprocess and Nanotechnology Conf. (MNC2012), (2012).
4. 4) N. Watanabe and T. Asano : Characteristics of a Novel Compliant Bump for 3-D Stacking with High-Density Inter-Chip Connections, IEEE Trans. Components, Packaging and Manufacturing Technology, 1 (2011) 83.
5. 5) N. Tanaka, Y. Yoshimura, T. Naito, C. Miyazaki, T. Uematsu, K. Hanada, N. Toma and T. Akazawa : Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding, Proc. Electronic Components Tech. Conf. (ECTC2006), (2006) 814.