High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering-Reference-Cited by-同舟云学术

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High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

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Container-title:IEEE International Electron Devices Meeting 2003
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Author:

Chan V.,Rengarajan R.,Rovedo N.,Wei Jin ,Hook T.,Nguyen P.,Jia Chen ,Nowak E.,Xiang-Dong Chen ,Lea D.,Chakravarti A.,Ku V.,Yang S.,Steegen A.,Baiocco C.,Shafer P.,Hung Ng ,Shih-Fen Huang ,Wann C.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8960/28396/01269170.pdf?arnumber=1269170

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology;IEEE Journal of the Electron Devices Society;2024

2. Principle, Structure, and Applications of Gallium Nitride High Electron Mobility Transistors (HEMTs);2023 19th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery (ICNC-FSKD);2023-07-29

3. Nano-MOSFET and Nano-CMOS;Nanoelectronics;2015-02-05

4. Strain induced changes in the gate leakage current of n-channel metal-oxide-semiconductor field-effect transistors;Journal of Applied Physics;2011-07

5. Hole mobility in silicon inversion layers: Stress and surface orientation;Journal of Applied Physics;2007-10-15

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