A Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-$\mu\hbox{m}$ CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/5592146/05456228.pdf?arnumber=5456228
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation;Electronics;2024-08-30
2. High Resolution ADC for Ultrasound Color Doppler Imaging Based on MASH Sigma-Delta Modulator;IEEE Transactions on Biomedical Engineering;2020-05
3. 4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit;IEEE Access;2020
4. A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer;Integration;2019-01
5. A 0.9-V 100- $\mu$ W Feedforward Adder-Less Inverter-Based MASH $\Delta\Sigma$ Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-11
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