An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS-Reference-Cited by-同舟云学术

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An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS

Published:2016-10 Issue:10 Volume:63 Page:1628-1638
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Nam Jae-Won^ORCID,Chen Mike Shuo-Wei

Funder

U.S. Office of Naval Research (ONR)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7577914/07524764.pdf?arnumber=7524764

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications;AEU - International Journal of Electronics and Communications;2024-01

2. A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping;IEEE Journal of Solid-State Circuits;2021-11

3. A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09

4. Design of a 16-bit 500-MS/s SAR-ADC for low-power application;Electronic Devices, Circuits, and Systems for Biomedical Applications;2021

5. A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer;IEEE Journal of Solid-State Circuits;2020-03

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