A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors-Reference-Cited by-同舟云学术

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

Published:2019-11 Issue:11 Volume:66 Page:4172-4185
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Si Xin^ORCID,Chang Meng-Fan^ORCID,Khwa Win-San^ORCID,Chen Jia-Jing,Li Jia-Fang,Sun Xiaoyu^ORCID,Liu Rui,Yu Shimeng^ORCID,Yamauchi Hiroyuki^ORCID,Li Qiang^ORCID

Funder

Taiwan Semiconductor Research Institute

Taiwan Semiconductor Manufacturing Company-Joint Development Program

MediaTek-Joint Development Program

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/8883027/08787897.pdf?arnumber=8787897

Cited by 115 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands;International Journal of Circuit Theory and Applications;2024-07-29

3. Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06

4. An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05

5. Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures;Microelectronic Engineering;2024-05