Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism-Reference-Cited by-同舟云学术

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Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism

Published:2013-04 Issue:4 Volume:60 Page:908-917
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ke Ji-Wei,Huang Shi-Yu,Tzeng Chao-Wen,Kwai Ding-Ming,Chou Yung-Fa

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/6486561/06298052.pdf?arnumber=6298052

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

2. A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-05

3. Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-06

4. An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications;Microelectronics Journal;2017-12

5. DLL-Assisted Clock Synchronization Method for Multi-Die ICs;2017 IEEE International Conference on Computer Design (ICCD);2017-11

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