A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/6339093/06184348.pdf?arnumber=6184348
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of a Low-Jitter 5.4 Gbps Half-Rate Clock and Data Recovery Circuit for eDP Application;2024 10th International Conference on Applied System Innovation (ICASI);2024-04-17
2. A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector;Analog Integrated Circuits and Signal Processing;2024-01-25
3. A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop;IEICE Electronics Express;2020-10-25
4. A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08
5. A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop;IEICE Electronics Express;2014
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