A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s10470-023-02242-z.pdf
Reference14 articles.
1. Razavi, B. (2012). Design of integrated circuits for optical communications. John Wiley and Sons.
2. Savoj, J., & Razavi, B. (2001). A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE Journal of Solid-State Circuits,36(5), 761–768.
3. Hsieh, M. T., & Sobelman, G. E. (2008). Architectures for multi-gigabit wire-linked clock and data recovery. IEEE Circuits and Systems Magazine,8(4), 45–57.
4. Razavi, B. (2002). Challenges in the design high-speed clock and data recovery circuits. IEEE Communications Magazine,40(8), 94–101.
5. Lee, W. Y., & Kim, L. S. (2012). A 5.4-Gb/s clock and data recovery circuit using seamless loop transition scheme with minimal phase noise degradation. IEEE Transactions on Circuits and Systems I: Regular Papers,59(11), 2518–2528.
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