Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8369410/08246734.pdf?arnumber=8246734
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Effect of annealing residual stress on mobility of TSV vertical switch;IEICE Electronics Express;2024-05-25
2. Signal Integrity Analysis of Through-Silicon-Via (TSV) With Passive Equalizer to Separate Return Path and Mitigate the Inter-Symbol Interference (ISI) for Next Generation High Bandwidth Memory;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-12
3. Deep Reinforcement Learning-Based Optimal and Fast Hybrid Equalizer Design Method for High-Bandwidth Memory (HBM) Module;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-11
4. Signal and Power Integrity Co-Simulation of HBM Interposer in High Density 2.5D Package;2022 23rd International Conference on Electronic Packaging Technology (ICEPT);2022-08-10
5. A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory;Micromachines;2022-07-05
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