Author:
Feng Xiaowen,Jin Hai,Zheng Ran,Hu Kan,Zeng Jingxiang,Shao Zhiyuan
Cited by
33 articles.
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1. Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07
2. Optimization Techniques for GPU Programming;ACM Computing Surveys;2023-03-16
3. AlphaSparse: Generating High Performance SpMV Codes Directly from Sparse Matrices;SC22: International Conference for High Performance Computing, Networking, Storage and Analysis;2022-11
4. A Ternary Neural Network with Compressed Quantized Weight Matrix for Low Power Embedded Systems;Engineering, Technology & Applied Science Research;2022-04-09
5. Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures;2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2021-03