Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously-Reference-Cited by-同舟云学术

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Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously

Published:2011-03 Issue: Volume: Page:
ISSN:
Container-title:2011 12th International Symposium on Quality Electronic Design
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Author:

Li Li,Choi Ken,Nan Haiqing

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5764309/5770683/05770706.pdf?arnumber=5770706

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low Power Implementation of 32-Bit RISC Processor with Pipelining;Lecture Notes in Electrical Engineering;2018-07-31

2. MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis;IET Computers & Digital Techniques;2018-04-11

3. Fuzzy c -mean clustering-based decomposition with GA optimizer for FSM synthesis targeting to low power;Engineering Applications of Artificial Intelligence;2018-02

4. Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling;Integration;2015-06

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