A systematic approach to modeling and analysis of transient faults in logic circuits
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4804412/4810250/04810329.pdf?arnumber=4810329
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. Remodelling correlation: A fault resilient technique of correlation sensitive stochastic designs;Array;2022-09
3. DAMSEL—Dynamic and Applicative Measurement of Single Events in Logic;IEEE Transactions on Nuclear Science;2018-01
4. SER Analysis of Multiple Transient Faults in Combinational Logic;Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference on - SEEDA-CECNSM '16;2016
5. Cross-layer custom instruction selection to address PVTA variations and soft error;Microelectronics Reliability;2015-11
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