An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process-Reference-Cited by-同舟云学术

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An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
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Author:

Tian Yuanxin¹,Zhang Yuejun¹,Zhang Huihong¹,Wen Liang²,Wang Pengjun³,Li Zhiyi¹

Affiliation:

1. Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315200

2. China Coast Guard Academy,Department of Electronic Technology,Ningbo,China,315200

3. Wenzhou University,College of Electrical and Electronic Engineering,Wenzhou,China,325035

Funder

National Natural Science Foundation of China

Science and Technology Innovation 2025 Major Project of Ningbo

Natural Science Foundation of Ningbo

Ningbo University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396468.pdf?arnumber=10396468

Reference9 articles.

1. A systematic approach to modeling and analysis of transient faults in logic circuits

2. Soft error immune latch under SEU related double-node charge collection

3. Propagation of Transients Along Sensitizable Paths

4. Construction of a soft error (SEU) hardened Latch with high critical charge

5. An SEU-Tolerant DICE Latch Design With Feedback Transistors

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