Impact of interconnect pattern density information on a 90 nm technology ASIC design flow

Author:

Zarkesh-Ha P.,Lakshminarayanan S.,Doniger K.,Loh W.,Wright P.

Publisher

IEEE Comput. Soc

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On the electrical properties of slotted metallic planes in CMOS processes for RF and millimeter-wave applications;Microelectronics Journal;2012-08

2. Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2011-11

3. Random Yield Prediction Based on a Stochastic Layout Sensitivity Model;IEEE Transactions on Semiconductor Manufacturing;2009-08

4. Metal-Density-Driven Placement for CMP Variation and Routability;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2008-12

5. DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances;IEEE Transactions on Semiconductor Manufacturing;2008

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