Timing driven multi-FPGA board partitioning-Reference-Cited by-同舟云学术

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Timing driven multi-FPGA board partitioning

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Container-title:Proceedings Eleventh International Conference on VLSI Design
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Author:

Burra R.,Bhatia D.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx3/5220/14112/00646609.pdf?arnumber=646609

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. High quality hypergraph partitioning for logic emulation;Integration;2022-03

4. Timing Driven Partition for Multi-FPGA Systems with TDM Awareness;Proceedings of the 2020 International Symposium on Physical Design;2020-03-20

5. ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-07

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