A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture-Reference-Cited by-同舟云学术

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A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Published:2015-11 Issue:11 Volume:50 Page:2635-2644
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wang Jinn-Shyan,Cheng Chun-Yuan,Chou Pei-Yuan,Yang Tzu-Yi

Funder

Ministry of Education

National Science Council, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7307914/07265106.pdf?arnumber=7265106

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display;Analog Integrated Circuits and Signal Processing;2023-11-10

2. A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

3. Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-01

4. A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC;Sensors;2021-12-31

5. A 0.75-5GHz Wide-Range 8-Phases Delay-Locked Loop With Low Noise Charge Pump;2021 16th International Conference on Computer Engineering and Systems (ICCES);2021-12-15

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