A 0.75-5GHz Wide-Range 8-Phases Delay-Locked Loop With Low Noise Charge Pump
Author:
Affiliation:
1. Mixel-Egypt,Cairo,Egypt
2. Ain Shams University,Faculty of Engineering,Electronics and Communications Engineering Department,Cairo,Egypt
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9685020/9686076/09686106.pdf?arnumber=9686106
Reference10 articles.
1. A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture
2. A 40 GHz DLL-based clock generator in 90 nm CMOS technology;chuang;IEEE ISSCC 20007 Dig Tech Papers,2007
3. 1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS
4. A wide-range delay-locked loop with a fixed latency of one clock cycle
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