A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique-Reference-Cited by-同舟云学术

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A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique

Published:2014-03 Issue:3 Volume:49 Page:708-717
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lin Wei-Te,Huang Hung-Yi,Kuo Tai-Haur

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6756988/06736139.pdf?arnumber=6736139

Cited by 69 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 12-Bit 1.2-GS/s Current-Steering DAC in 45-NM CMOS Technology;Journal of Circuits, Systems and Computers;2024-04-13

2. A 16-bit DPT-DAC over 120dBc SFDR with Signal-Phase regulation and Switching-Glitch neutralization;AEU - International Journal of Electronics and Communications;2024-03

3. A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

4. A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding;2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan);2023-07-17

5. Analysis and Modeling of System Performance Based on Random Matching Errors, Gradient Errors, and Finite Output Impedance of Current-source DAC;Journal of Physics: Conference Series;2023-06-01

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