A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding
Author:
Affiliation:
1. National Sun Yat-sen University,Dept. of Computer Science and Engineering,Kaohsiung,Taiwan
2. Institute of Information and Communication National Chung-Shan Institute of Science and Technology,Taoyuan,Taiwan
Funder
Ministry of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10226627/10226615/10226949.pdf?arnumber=10226949
Reference6 articles.
1. High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique
2. Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-$\mu$m CMOS
3. A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique
4. A 12GS/s 6-bit DAC with 4–2 Segmentation in 40nm CMOS
5. A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $70 dB SFDR up to 500 MHz
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