A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8118328/08068949.pdf?arnumber=8068949
Cited by 31 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop;Circuits, Systems, and Signal Processing;2023-08-10
2. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
3. A 14–28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
4. A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS;IEEE Journal of Solid-State Circuits;2023-05
5. A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02
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