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A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

  • Published:2012-11 Issue:11 Volume:47 Page:2614-2626
  • ISSN:0018-9200
  • Container-title:IEEE Journal of Solid-State Circuits
  • language:
  • Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhu Yan,Chan Chi-Hang,Sin Sai-Weng,U Seng-Pan,Martins Rui Paulo,Maloberti Franco

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

2. An input signal dependent 8-to-12 bit variable resolution SAR ADC with digitally implemented bit enhancement Logic;AEU - International Journal of Electronics and Communications;2023-08

3. A New Structure of 8-Bit 60 MS/s SAR-ADC Using a Reduced Switching Capacitor-DAC Array;Journal of Circuits, Systems and Computers;2021-10-06

4. A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09

5. A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05
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