A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme-Reference-Cited by-同舟云学术

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Published:2013-01 Issue:1 Volume:48 Page:168-177
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sohn Kyomin,Na Taesik,Song Indal,Shim Yong,Bae Wonil,Kang Sanghee,Lee Dongsu,Jung Hangyun,Hyun Seokhun,Jeoung Hanki,Lee Ki-Won,Park Jun-Seok,Lee Jongeun,Lee Byunghyun,Jun Inwoo,Park Juseop,Park Junghwan,Choi Hundai,Kim Sanghee,Chung Haeyoung,Choi Young,Jung Dae-Hee,Kim Byungchul,Choi Jung-Hwan,Jang Seong-Jin,Kim Chi-Wook,Lee Jung-Bae,Choi Joo Sun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6399535/06316063.pdf?arnumber=6316063

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