Architecting DDR5 DRAM caches for non-volatile memory systems-Reference-Cited by-同舟云学术

Architecting DDR5 DRAM caches for non-volatile memory systems

Published:2022-07-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 59th ACM/IEEE Design Automation Conference
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Author:

Xin Xin¹,Zhu Wanyi²,Zhao Li²

Affiliation:

1. University of Pittsburgh

2. Alibaba Group

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3489517.3530570

Reference18 articles.

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2. Z. Wang , , " Characterizing and Modeling Non-Volatile Memory Systems," in MICRO , 2020 . Z. Wang, et al., "Characterizing and Modeling Non-Volatile Memory Systems," in MICRO, 2020.

3. M. Qureshi , , " Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design," in MICRO , 2012 . M. Qureshi, et al., "Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design," in MICRO, 2012.

4. E. Vasilaki , , " Hybrid2: Combining Caching and Migration in Hybrid Memory Systems," in HPCA , 2020 . E. Vasilaki, et al., "Hybrid2: Combining Caching and Migration in Hybrid Memory Systems," in HPCA, 2020.

5. T. Lu , , " System measurement of Intel AEP Optane DIMM," in arXiv:2009.14469 , 2020 . T. Lu, et al., "System measurement of Intel AEP Optane DIMM," in arXiv:2009.14469, 2020.

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