A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation-Reference-Cited by-同舟云学术

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A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation

Published:2018-03 Issue:3 Volume:53 Page:799-813
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Dey Siladitya^ORCID,Reddy Karthikeyan,Mayaram Kartikeya,Fiez Terri S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8295182/08226985.pdf?arnumber=8226985

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mixed-Order Correlated Dual-Loop Sturdy MASH CT-$\Delta \Sigma $ Modulator With Distributed Signal Feed-In and VCO Quantizer;IEEE Journal of Solid-State Circuits;2024

2. A 62.5MHz Bandwidth Third-Order VCO-based Sigma-Delta ADC with a Hybrid Architecture;Proceedings of the 2023 6th International Conference on Electronics, Communications and Control Engineering;2023-03-24

3. High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers;IEEE Open Journal of the Solid-State Circuits Society;2023

4. A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based ΔΣ Modulators;IEEE Journal of Solid-State Circuits;2022-12

5. An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-12

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