A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s-Reference-Cited by-同舟云学术

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A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s

Published:2018-05 Issue:5 Volume:53 Page:1493-1507
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

AlMarashli Ahmad^ORCID,Anders Jens,Becker Joachim^ORCID,Ortmanns Maurits^ORCID

Funder

German Research Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8345343/08207772.pdf?arnumber=8207772

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

2. A hybrid SAR ADC with input range extension;Microelectronics Journal;2024-08

3. Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones;Journal of Physics: Conference Series;2024-04-01

4. A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS;AEU - International Journal of Electronics and Communications;2024-02

5. A 16-bit 1-MS/s SAR ADC With Asynchronous LSB Averaging Achieving 95.1-dB SNDR and 98.1-dB DR;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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