Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access-Reference-Cited by-同舟云学术

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Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Published:2014-01 Issue:1 Volume:49 Page:107-117
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sinangil Mahmut E.,Chandrakasan Anantha P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6690141/06605621.pdf?arnumber=6605621

Cited by 36 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploiting Neural-Network Statistics for Low-Power DNN Inference;IEEE Open Journal of Circuits and Systems;2024

2. Design of Low Power PMOS Biased Sense Amplifier Using Lector Approach;2022 8th International Conference on Smart Structures and Systems (ICSSS);2022-04-21

3. A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications;Semiconductor Science and Technology;2022-03-17

4. Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-11

5. SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC);2021-09-13

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