Design of Low Power PMOS Biased Sense Amplifier Using Lector Approach
Author:
Affiliation:
1. Prathyusha Engineerinng College,Dept of ECE,TamilNadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9782157/9782158/09782187.pdf?arnumber=9782187
Reference17 articles.
1. Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
2. A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access
3. Comparative Analysis of Sense Amplifiers for Memories A;HEMAPRABHA Electronics and Communication Engineering Manakula Vinayagar Institute of Technology Kalitheerthalkuppam India olihema995 gmail com K VIVEK Electronics and Communication Engineering Manakula Vinayagar Institute of Technology Kalitheerthalkuppam,0
4. Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)
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