Author:
Chandrakasan A.P.,Daly D.C.,Finchelstein D.F.,Kwong J.,Ramadass Y.K.,Sinangil M.E.,Sze V.,Verma N.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
78 articles.
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1. Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
2. A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
3. An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
4. Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-07
5. Per-Core Configurable Power Supply for Multi-Core Processors with Ultra-Fast DVS Voltage Transitions;2022 IEEE Applied Power Electronics Conference and Exposition (APEC);2022-03-20