A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits
Author:
Affiliation:
1. ETH Zurich,Department of Information Technology and Electrical Engineering,Zurich,Switzerland
2. School of Computer and Communication Sciences,Ecole Polytechnique Fédérale de Lausanne (EPFL),Lausanne,Switzerland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10035104/10035106/10035122.pdf?arnumber=10035122
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
2. Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
3. High-Level Synthesis;FPGA EDA;2024
4. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
5. MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
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