15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node
Author:
Affiliation:
1. Yonsei University,Seoul,Korea
Funder
National Research Foundation of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454360.pdf?arnumber=10454360
Reference5 articles.
1. A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications
2. Roadmap report: More Moore,2021
3. 24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit
4. A 7 nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications;Song
5. SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling
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