10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fs<sub>rms</sub> Jitter, -253.5dB FoM<sub>J</sub>, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment-Reference-Cited by-同舟云学术

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fs_rms Jitter, -253.5dB FoM_J, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment

Published:2024-02-18 Issue: Volume: Page:204-206
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
language:
Short-container-title:

Author:

Li Haoran¹,Xu Tailong¹,Meng Xi¹,Yin Jun¹,Martins Rui P.¹,Mak Pui-In¹

Affiliation:

1. University of Macau,Macau,China

Funder

Technology Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454298.pdf?arnumber=10454298

Reference7 articles.

1. 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

2. A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fs_rms Jitter, -252.8dB FoM_J, and Robust Lock Acquisition Performance

3. 17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

4. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

5. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

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