11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint
Author:
Wu Tony F.1,
Liu Huichu1,
Sumbul H. Ekin1,
Yang Lita1,
Baheti Dipti1,
Coriell Jeremy1,
Koven William1,
Krishnan Anu1,
Mittal Mohit1,
Moreira Matheus Trevisan1,
Waugaman Max1,
Ye Laurent1,
Beigné Edith1